FIG. 10(a) is a perspective view illustrating an external structure of a prior art semiconductor package, FIG. 10(b) is a sectional view taken along a line 10b--10b of FIG. 10(a), and FIG. 10(c) is a sectional view taken along a line 10c--10c of FIG. 10(a). FIG. 11(a) is a perspective view illustrating an internal structure of the semiconductor package, FIG. 11(b) is an enlarged view of a portion "A" of FIG. 10(b), and FIG. 11(c) is a plan view illustrating a front surface of a package substrate on which the semiconductor package is to be mounted. FIG. 12 is an exploded perspective view of the semiconductor package. FIG. 13(a) is a perspective view illustrating a rear surface of the semiconductor package.
In these figures, reference numeral 200 designates a semiconductor package containing a semiconductor chip 29 and mounted on a package substrate (printed board) 1. The semiconductor package 200 includes a plurality of external lead terminals 5 arranged on prescribed opposite sides of the package 200, a package body 201 containing the semiconductor chip 29, and a lid 4 comprising a metal plate. The lid 4 covers an opening of the package body 201 and hermetically seals the semiconductor chip 29 in the package body 201.
The package body 201 includes a base substrate 3 having opposite front and rear surfaces. Ground conductors 3a and 3b are disposed on the front surface and the rear surface of the base substrate 3, respectively. A plurality of through-holes 22 penetrate through the base substrate 3 and connect the front side ground conductor 3a to the rear side ground conductor 3b. A semiconductor chip 29 is disposed on the front side ground conductor 3a. A first ceramic frame 20 is disposed on the front surface of the base substrate 3, surrounding the semiconductor chip 29. A plurality of conductive layers 20a are disposed on the surface of the first ceramic frame 20. A second ceramic frame 21 is disposed on the first ceramic frame 20. A metal film 21a is disposed on the second ceramic frame 21. The external lead terminals 5 are soldered to portions of the conductive layers 20a on the first ceramic frame 20 outside the second ceramic frame 21. The lid 4 is soldered to the second ceramic frame 21 with a solder 33.
As shown in FIG. 11(b), the conductive layer 3b on the rear surface of the base substrate 3 comprises a metallized layer 111 in contact with the base substrate, a plated Ni layer 112 disposed on the metallized layer 111, and a plated Au layer 113 disposed on the plated Ni layer 112. The size of the base substrate 3 is the same as the size of the ceramic frame 20. On the side surfaces of the base substrate 3 and the ceramic frame 20 where the external lead terminals 5 are absent, metal films 3c and 20b are disposed, respectively. These metal films 3c and 20b have the same layer structure as the conductive layer 3b.
In the semiconductor package 200 having the above-described structure, as shown in FIG. 11(a), the semiconductor chip 29 is fixed to the conductive layer 3a on the front surface of the base substrate 3 with solder 31, and the chip 29 is connected to the external lead terminals 5 through bonding wires 30.
Further, as illustrated in FIG. 11(c), a solder land 2 comprising a metallized layer is disposed on a region of the package substrate 1 where the semiconductor package 200 is to be mounted. A plurality of conductive layers 25 are disposed on the package substrate 1 at positions opposite the external lead terminals 5 of the semiconductor package 200. When the semiconductor package 200 is mounted on the package substrate 1, the external lead terminals 5 are in contact with the respective conductive layers 25. Solder films are printed on the solder land 2 and on the conductive layers 25.
A description is given of the fabrication process of the semiconductor package 200.
Initially, the base substrate 3 having the conductive layers 3a, 3c, and 3b on the front, side, and rear surfaces, respectively, and the through-holes 22 connecting the conductive layer 3a on the front surface to the conductive layer 3b on the rear surface is prepared. Then, the second ceramic frame 21 having the metal film 21a on its front surface is put on the first ceramic frame 20 with the conductive layers 20a and 20b respectively on the front and side surfaces, and the first ceramic frame 20 is put on the base substrate 3, followed by baking to fix the frames on the base substrate 3 (refer to FIG. 12).
Thereafter, the external lead terminals 5 are connected to the conductive layers 20a of the first ceramic frame 20 with solder, completing the package body 201.
Generally, the semiconductor package body 201 is offered to users, and a semiconductor chip is mounted on the semiconductor package at the user's end.
More specifically, at the user's end, the semiconductor chip 29 is put on the package body 201 so that the chip 29 is in contact with the conductive layer 3a of the base substrate 3, and the chip 29 is fixed to the base substrate 3 with solder 31. The semiconductor chip 29 is connected to the external lead terminals 5 of the package 200 with bonding wires 30. Thereafter, the package lid 4 is soldered to the second ceramic frame 21, whereby the semiconductor chip 29 is hermetically sealed in the semiconductor package 200.
The semiconductor package 200 is positioned on the solder land 2 of the package substrate 1 so that the external lead terminals 5 are in contact with the corresponding conductive layers 25 at the end portions of the conductive layers 25. Thereafter, the solder land 2 and the solder layers 6 on the conductive layers 25 are melted by thermal treatment, whereby the semiconductor package 200 is fixed to the solder land 2 and the external lead terminals 5 are fixed to the conductive layers 25.
After the above-described mounting process, whether the connection between the semiconductor package 200 and the package substrate 1 through the solder 6 is good or bad is determined by inspecting for the inspected by existence of solder fillets 9 on the both sides of the package where the external lead terminals 5 are absent. More specifically, since Au having a good adhesion with the solder is plated on the conductive layer 3c on the side surface of the package 200, if the conductive layer 3b on the rear surface of the package 200 is in good contact with the solder land 2 of the package substrate 1, the solder swells at the side surface of the package due to surface tension, so that the solder fillet 9 is produced.
The reason why the above-described inspection of the connection between the semiconductor package 200 and the package substrate 1 is necessary is as follows. If the adhesion between the rear side conductive layer 3b of the package body 201 and the solder land 2 of the package substrate 1 is insufficient, the package body is not in good contact with the package substrate 1, so that the contact resistance increases. In addition, radiation of heat produced in the semiconductor chip 29 is degraded, whereby the semiconductor chip 29 is excessively heated, resulting in imperfect oscillation and degraded high-frequency characteristics of the semiconductor device.
In the above-described prior art semiconductor package 200, since the plated Au layer 113 on the conductive layer 3b disposed on the rear surface of the package body 201 has good adhesion to solder, when the semiconductor package 200 mounted on the solder land 2 of the package substrate 1 is subjected to thermal treatment, the solder. 6 printed on the solder land 2 melts and unfavorably flows toward the center of the rear surface of the package body 201, so that the solder fillet 9 for the quality inspection is not produced on the side surface of the semiconductor package 200.
This unwanted flow of the solder on the rear surface of the semiconductor package is a result of the plated Au layer 113 on the rear surface of the package body that is partially decreased due to diffusion of Au into the solder layer 6, and the solder 6 flows into that portion of the plated Au layer 113. In this case, as shown in FIG. 13(b), the solder 6 does not protrude at the side surface of the package body where the conductive layers 3c and 20b are present, and the solder fillet 9 is not produced.
As the result, after the mounting of the semiconductor package 200 on the package substrate 1, the adhesion between the conductive layer 3b on the rear surface of semiconductor package and the solder land 2 on the front surface of the package substrate 1 cannot be inspected, thereby reducing the reliability of the semiconductor device.